Design Considerations and Comparative Investigation of Ultra-Thin SOI, Double-Gate and Cylindrical Nanowire FETs

Author

Gnani, E. ; Reggiani, S. ; Rudan, M. ; Baccarani, G.

Author_Institution

ARCES & DEIS, Bologna Univ.

fYear

2006

fDate

Sept. 2006

Firstpage

371

Lastpage

374

Abstract

In this work we investigate the performance of fully-depleted silicon-on-insulator (SOI), double-gate (DG) and cylindrical nanowire (CNW) FETs, with the aim of establishing optimization procedures and appropriate scaling rules towards their extreme miniaturization limits. The simulation model fully accounts for quantum electrostatics; current transport is modeled by an improved quantum drift-diffusion approach supported by a new thickness-dependent mobility model which nicely fits the available measurements. The simple rule resulting from this investigation is that stringent short-channel effect constraints can be fulfilled at a constant oxide thickness of 2 nm, with L_g/t _Si ap 5 for the SOI-FET, L_g/t_Si ap 2 for the DG-FET, and L_g /t_Si ap 1 for the CNW-FET

Keywords

diffusion; electrostatics; field effect transistors; nanowires; semiconductor device models; silicon-on-insulator; 2 nm; constant oxide thickness; current transport; cylindrical nanowire FET; double-gate FET; fully-depleted silicon-on-insulator FET; quantum drift-diffusion approach; quantum electrostatics; short-channel effect constraints; thickness-dependent mobility model; ultra-thin SOI FET; CMOS technology; Design optimization; Double-gate FETs; Electrons; Electrostatics; FinFETs; Poisson equations; Predictive models; Quantum computing; Silicon on insulator technology;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Device Research Conference, 2006. ESSDERC 2006. Proceeding of the 36th European

Conference_Location

Montreux

ISSN

1930-8876

Print_ISBN

1-4244-0301-4

Type

conf

DOI

10.1109/ESSDER.2006.307715

Filename

4099933