Double Gate Tunnel FET with ultrathin silicon body and high-k gate dielectric

In this paper we propose a novel design for a double gate tunnel field effect transistor (DG TFET), for which the simulations show significant improvements compared with single gate devices with a SiO ₂ gate dielectric. For the first time, double gate devices using a high-K gate dielectric are explored, showing on-current as high as 1 mA for a gate voltage of 1.2 V, reduced off-current as low as 0.1 fA, improved average subthreshold swing of 52 mV/decade, and a minimum point slope of 18 mV/decade. An Ion/Ioff ratio of more than 10¹² is shown