Does Multi-Trap Assisted Tunneling explain the oxide thickness dependence of the Statistics of SILC in FLASH Memory Arrays?

Author

Vianello, E. ; Driussi, F. ; Esseni, D. ; Selmi, L. ; van Duuren, M.J. ; Widdershoven, F.

Author_Institution

DIEGM, Udine Univ.

fYear

2006

fDate

Sept. 2006

Firstpage

403

Lastpage

406

Abstract

In this paper, we analyze the experimental SILC statistical data at low stress reported in (Driussi et al., 2005) . To this purpose we developed an analytical physical model to study the statistical distribution of the TAT current due to single and multiple traps in the gate oxide of a floating gate memory cell. We modeled also the generation dynamics of conductive percolation paths due to more traps and we simulated the SILC statistical distribution in the memory cell. This study points out the differences in the statistical behavior of the TAT current due to defects formed by single and multiple traps

Keywords

flash memories; leakage currents; statistical distributions; tunnelling; FLASH memory arrays; analytical physical model; floating gate memory cell; multiple traps; multitrap assisted tunneling; single traps; statistical distribution; stress induced leakage current; trap assisted tunneling current; Analytical models; Flash memory; Lead compounds; Leakage current; Nonvolatile memory; Photonic band gap; Statistical distributions; Statistics; Stress; Tunneling;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Device Research Conference, 2006. ESSDERC 2006. Proceeding of the 36th European

Conference_Location

Montreux

ISSN

1930-8876

Print_ISBN

1-4244-0301-4

Type

conf

DOI

10.1109/ESSDER.2006.307723

Filename

4099941