A Study of the As-Processed and Generated Leakage Paths in Al2O3-Based Dielectric Stacks for Nonvolatile Memory Applications

Author

Ruiz Aguado, D. ; Govoreanu, B. ; Degraeve, R. ; Van Houdt, J. ; De Meyer, K.

Author_Institution

IMEC, Leuven

fYear

2006

fDate

19-21 Sept. 2006

Firstpage

407

Lastpage

410

Abstract

Continued shrinkage of floating gate devices requires scaling of the tunnel and/or interpoly dielectrics. This leads to increasing leakage currents that jeopardize the nonvolatile memory retention requirements. High-k materials are natural candidates to enable further scaling of the tunnel/interpoly dielectrics. In this paper, we present an analysis of the defects in Al₂O₃-based stacks. It is found that stacks with a deposited bottom SiO₂ layer follow a two-step path generation trend, while the presence of a thin interfacial layer leads to a weaker path creation. Furthermore, the effect of the post-deposition anneal is also discussed

Keywords

aluminium compounds; annealing; dielectric materials; leakage currents; random-access storage; silicon compounds; Al₂O₃; SiO₂; dielectric stacks; floating gate devices; high-k materials; interfacial layer; interpoly dielectrics; leakage currents; nonvolatile memory; post-deposition anneal; tunnel dielectrics; Aluminum oxide; Annealing; CMOS technology; Dielectric devices; Dielectric materials; Flash memory; High K dielectric materials; High-K gate dielectrics; Leakage current; Nonvolatile memory;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Device Research Conference, 2006. ESSDERC 2006. Proceeding of the 36th European

Conference_Location

Montreux

ISSN

1930-8876

Print_ISBN

1-4244-0301-4

Type

conf

DOI

10.1109/ESSDER.2006.307724

Filename

4099942