A New Motion Estimation Architecture For Block-Matching Algorithm

In this paper, a new architecture for a motion estimator with full search capability, based on simplified pixel difference classification (PDC) algorithm is presented. Based on the proposed approach for matching criteria, and enhanced by the fixed pixel threshold technique, the hardware requirement for every single processing element was reduced at a ratio of 30~40% compared with the implementation of conventional algorithms. This circuit is designed for a block size of 16 times 16 pixels, and search area -8/7. , It can be cascaded by 4 such circuit for a search range of -16 / 15. It allows sequential inputs but performs parallel computations. At 100 MHz clock rate, it needs 2.5 usec to finish calculating one motion vector. Realized by TSMC 0.18 mum CMOS technology, it has a core area of .01 mm².