Evaluating the training dynamics of a CMOS based synapse

Recent work by the authors proposed compact low power synapses in hardware, based on the charge-coupling principle, that can be configured to yield a static or dynamic response. The focus of this work is to investigate the training dynamics of these synapses. Empirical models of the Post Synaptic Response (PSP), derived from hardware simulations, were developed and subsequently embedded into the MATLAB environment. A network of these synapses was then used to solve a benchmark problem using a well established training algorithm where the performance metric was convergence time, accuracy and weight range; the Spike Response Model (SRM) was used to implement point neurons. Results are presented and compared with standard synaptic responses.