DocumentCode
3495163
Title
A 0.7-to-1.1-GHz all-digital phase-locked loop with a new phase frequency detector and controlled oscillator with body-biasing
Author
Shabaany, Mohammad Hassan ; Saneei, Mohsen
Author_Institution
Dept. of Electr. & Comput. Eng., Grad. Univ. of Technol., Kerman, Iran
fYear
2012
fDate
2-3 May 2012
Firstpage
54
Lastpage
59
Abstract
A 0.7-to-1.1-GHz all-digital phase locked loop with a new phase frequency detector and controlled oscillator with body-biasing is presented. Digital-to-voltage converter is controlled the bulk voltage in proposed voltage controlled oscillator, which results high frequency resolution and low power consumption. A search algorithm is used to generates the digital code for the digital-to-voltage converter. This all-digital phase locked loop uses a new structure for the phase-frequency-detector, which ensures high accuracy at phase frequency detecting and increasing lock speed. The proposed design is evaluated in PTM 65nm. The power consumption of the proposed circuit at 900 MHz frequency is 4.8mW.
Keywords
digital phase locked loops; logic gates; oscillators; sensors; all-digital phase-locked loop; body-biasing; bulk voltage; controlled oscillator; digital code; digital-voltage converter; frequency 0.7 GHz to 1.1 GHz; phase frequency detector; power consumption; voltage controlled oscillator; Clocks; Delay; Frequency control; Oscillators; Phase frequency detector; Phase locked loops; Shift registers; All digital phase lock loop (ADPLL); digitally controlled oscillator; frequency synthesizer; phase frequency detector;
fLanguage
English
Publisher
ieee
Conference_Titel
Computer Architecture and Digital Systems (CADS), 2012 16th CSI International Symposium on
Conference_Location
Shiraz, Fars
Print_ISBN
978-1-4673-1481-7
Type
conf
DOI
10.1109/CADS.2012.6316419
Filename
6316419
Link To Document