A high performance, race eliminated, two phase nonoverlapping clocked All-N-Logic for both strong and subthreshold designs

In this paper, a new structure of ANL logic, named TPANL, is presented to achieve higher performance, lower power consumption and eliminating glitches. Different ANL logics suffer from output glitches due to race problem. Our proposed TPANL logic by two phase nonoverlapping clocks eliminates output glitches and reduces glitch power. TPANL logic speedup is mainly due to reduced capacitance at each evaluation node of a dynamic circuit. This logic works in both operational region of strong inversion and subthreshold region, with 10GHz to 12.5MHz respectively. In spite of NonInv./Inv. pipeline in ANL logics, TPANL is based on NonInv./NonInv. pipeline and therefore it solves the voltage drops on NMOS Inv. stages in subthreshold regions. The simulation results of 4-bit CLA adder show 27% and 72.9% power consumption reduction, also, 60% and 50% performance improvement, in strong inversion region rather than ANL and DPANL respectively. The 4-bit CLA adder with TPANL logic in the subthreshold region has about 92nW power consumption.