• DocumentCode
    3495314
  • Title

    A new technique for high speed decimal logarithm computation of decimal floating-point number

  • Author

    Khan, Kazi Muhammad Najmul Hasan ; Ali, Md Liakot ; Islam, Sabrin

  • Author_Institution
    Inst. of Inf. & Commun. Technol., BUET, Dhaka, Bangladesh
  • fYear
    2011
  • fDate
    22-24 Dec. 2011
  • Firstpage
    208
  • Lastpage
    212
  • Abstract
    This paper presents a new design and a fast technique for implementation of a 32-bit decimal floating-point (DFP) logarithmic computation to efficiently calculate radix-10 logarithm of a decimal number. Conventional techniques first convert decimal inputs to binary, then perform base-2 logarithm operations, and finally results are converted back to decimal radix. It sometimes causes errors due to the back and forth conversions of the bases. The technique described in this paper uses a 32-bit floating-point arithmetic, and utilizes only addition and subtraction operations. It does not require any decimal to binary conversion, or division operation. As a result, the described algorithm offers a low-cost, hardware-efficient and lower power consumption method for computing decimal floating-point numbers.
  • Keywords
    floating point arithmetic; power consumption; addition operations; base-2 logarithm operations; decimal floating-point logarithmic computation; decimal floating-point number; decimal radix; floating-point arithmetic; high speed decimal logarithm computation; power consumption method; radix-10 logarithm calculation; subtraction operations; Algorithm design and analysis; Convergence; Hardware; Decimal logarithm; FPGA; VLSI; radix-10 floating-point arithmetic;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Computer and Information Technology (ICCIT), 2011 14th International Conference on
  • Conference_Location
    Dhaka
  • Print_ISBN
    978-1-61284-907-2
  • Type

    conf

  • DOI
    10.1109/ICCITechn.2011.6164785
  • Filename
    6164785