A GF(24m) Inverter and its Application in a Reconfigurable Tate Pairing Processor

Author

Keller, Maurice ; Ronan, Robert ; Marnane, William ; Murphy, Colin

Author_Institution

Dept. of Electr. & Electron. Eng., Univ. Coll. Cork

fYear

2006

fDate

Sept. 2006

Firstpage

1

Lastpage

10

Abstract

This paper details an architecture for performing inversion in the field GF(2^4m), which is the field used in computing the Tate pairing on characteristic 2 supersingular elliptic curves. The inverter architecture is then used to improve the performance of a reconfigurable Tate pairing hardware accelerator. Implementation results for the improved processor on an FPGA are presented and compared to those of the basic processor without the inverter

Keywords

Galois fields; field programmable gate arrays; public key cryptography; reconfigurable architectures; FPGA; inverter architecture; reconfigurable Tate pairing hardware accelerator; reconfigurable Tate pairing processor; supersingular elliptic curves; Acceleration; Computer architecture; Elliptic curve cryptography; Elliptic curves; Field programmable gate arrays; Hardware; Identity-based encryption; Inverters; Public key; Public key cryptography;

fLanguage

English

Publisher

ieee

Conference_Titel

Reconfigurable Computing and FPGA's, 2006. ReConFig 2006. IEEE International Conference on

Conference_Location

San Luis Potosi

Print_ISBN

1-4244-0690-0

Electronic_ISBN

1-4244-0690-0

Type

conf

DOI

10.1109/RECONF.2006.307766

Filename

4099986