Title :
On the reliability of switching and multivalued networks
Author :
Abbasinasab, Ali ; Yanushkevich, S.N.
Author_Institution :
Dept. of Electr. & Comput. Eng., Univ. of Calgary, Calgary, AB, Canada
Abstract :
This paper investigates reliability of logic gates and circuits based on probabilistic transfer matrices (PTM). A probabilistic model for multivalued gates and networks is developed through extending the concept of PTM. This paper studies how the reliability of k-ary logic networks depends on the radix k and the input and gate errors.
Keywords :
circuit reliability; logic gates; matrix algebra; multivalued logic circuits; probability; PTM; gate errors; k-ary logic networks; logic circuits; logic gate reliability; multivalued gates; multivalued networks; probabilistic model; probabilistic transfer matrices; Benchmark testing; Error probability; Integrated circuit reliability; Logic gates; Noise; Probabilistic logic; multivalued logic; probabilistic transfer matrices; reliability analysis; switching circuit;
Conference_Titel :
Computer Architecture and Digital Systems (CADS), 2012 16th CSI International Symposium on
Conference_Location :
Shiraz, Fars
Print_ISBN :
978-1-4673-1481-7
DOI :
10.1109/CADS.2012.6316437
