DocumentCode :
3495554
Title :
Gate Diffusion Input (GDI) logic in standard CMOS nanoscale process
Author :
Morgenshtein, Arkadiy ; Shwartz, Idan ; Fish, Alexander
Author_Institution :
Dept. of Electr. & Comput. Eng., Ben-Gurion Univ., Beer-Sheva, Israel
fYear :
2010
fDate :
17-20 Nov. 2010
Abstract :
In this paper CMOS compatible Gate Diffusion Input (GDI) design technique is proposed. The GDI method enables the implementation of a wide range of complex logic functions using only two transistors. This method is suitable for the design of low-power logic gates, with a much smaller area than Static CMOS and existing PTL techniques. As opposite to our originally proposed GDI logic, the modified GDI logic is fully compatible for implementation in a standard CMOS process. Simulations of basic GDI gates under process and temperature corners in 40nm CMOS process are shown and compared to similar CMOS gates. We show that while having the same delay, GDI gates achieve leakage and active power reduction of up to 70% and 50%, respectively.
Keywords :
CMOS logic circuits; logic design; logic gates; low-power electronics; gate diffusion input design; gate diffusion input logic; logic functions; low-power logic gates; size 40 nm; standard CMOS nanoscale process; static CMOS; CMOS integrated circuits; CMOS process; Leakage current; Logic gates; Semiconductor device modeling; Threshold voltage; Transistors; GDI; Gate Diffusion Input; low power digital design; pass-transistor logic;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electrical and Electronics Engineers in Israel (IEEEI), 2010 IEEE 26th Convention of
Conference_Location :
Eliat
Print_ISBN :
978-1-4244-8681-6
Type :
conf
DOI :
10.1109/EEEI.2010.5662107
Filename :
5662107
Link To Document :
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