Power ground-reference plane decoupling analysis of design alternatives

The increase in processor and signal speeds has made the performance of various power and ground-reference plane decoupling strategies has been a major concern in the design of printed circuit boards (PCB). While there has been a number of articles written concerning analyzing the performance of power ground-reference planes, little experimental work with actual PCB has been reported, mostly due to the difficulty in making clearly defined measurements of the effect of decoupling capacitors. This work demonstrates the effect of decoupling capacitors on a typical Pentium processor PCB in both the time domain and the frequency domain. This analysis allows engineers to examine the decoupling performance for both functionality issues and EMC issues. Simulations using the partial element equivalent circuit (PEEC) technique are combined with careful measurements to show the effects of a variety of different decoupling alternatives