A 0.7 μm linear BiCMOS/DMOS technology for mixed-signal/power applications

Author

Smith, Jeffrey ; Tessmer, Alison ; Springer, Lily ; Madhani, Praful ; Erdeljac, John ; Mitros, Jozef ; Efland, Taylor ; Tsai, Chin-Yu ; Pendharkar, Sameer ; Hutter, Louis

Author_Institution

Texas Instrum. Inc., Dallas, TX, USA

fYear

1997

fDate

28-30 Sep 1997

Firstpage

155

Lastpage

157

Abstract

A 0.7 μm BiCMOS technology is described. The baseline process offers digital and analog CMOS, a variety of bipolar devices, poly resistors, poly-poly capacitors, Schottky diodes, noise isolation, and 3 levels of metal. Power DMOS transistors with 60 V (R_sp=0.90 mΩ·cm²) down to 16 V (R_sp=0.34 mΩ·cm²) performance are available as an option in the process

Keywords

BiCMOS integrated circuits; integrated circuit noise; integrated circuit technology; mixed analogue-digital integrated circuits; power integrated circuits; 0.7 micron; 16 to 60 V; Schottky diodes; analog CMOS; bipolar devices; digital CMOS; linear BiCMOS/DMOS technology; mixed-signal/power applications; noise isolation; poly resistors; poly-poly capacitors; power DMOS transistors; BiCMOS integrated circuits; CMOS process; CMOS technology; Capacitors; Costs; Isolation technology; Logic; MOS devices; Noise level; Printers; Resistors; Schottky diodes; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Bipolar/BiCMOS Circuits and Technology Meeting, 1997. Proceedings of the

Conference_Location

Minneapolis, MN

ISSN

1088-9299

Print_ISBN

0-7803-3916-9

Type

conf

DOI

10.1109/BIPOL.1997.647424

Filename

647424