Priority performance of ATM packet switches

An asynchronous transfer mode (ATM) packet switch should be capable of handling delay sensitive as well as loss sensitive traffic. The authors consider delinking handling of these two types of priorities in a switching system, and present an analysis of two classes of delay sensitive traffic in an N×N nonblocking switch with input queues. In such a switch, two variations of nonpreemptive priority are studied. A packet switch with input buffers has inadequate throughput. To enhance the performance and to provide low delay to high priority traffic, a dual plane switch architecture is examined, where each plane is a nonblocking switch with input buffers. The two planes are connected in parallel to form a load sharing arrangement. The analysis of a single plane nonblocking switch is extended to this architecture. In both cases, the performance is compared with the simulation results of a 64×64 switch