Title :
A quasi delay-insensitive bus proposal for asynchronous systems
Author :
Molina, Pedro A. ; Cheung, Peter Y K
Author_Institution :
Dept. of Electr. & Electron. Eng., Imperial Coll. of Sci., Technol. & Med., London, UK
Abstract :
The composability dimension of asynchronous circuits is extended to incorporate delay-insensitivity, area utilisation and layout complexity. The disadvantages of conventional delay-insensitive data paths are established, and an alternative solution based on tri-state buffers is presented. The solution maintains the same delay-insensitivity while achieving a significant reduction in circuit area utilisation and layout complexity of the data path
Keywords :
asynchronous circuits; logic design; minimisation of switching nets; area utilisation; asynchronous circuits; data path; delay-insensitive bus; layout complexity; tri-state buffers; Circuit testing; Delay systems; Impedance; Logic design; Logic testing; Proposals; Routing; Signal design; Very large scale integration; Wire;
Conference_Titel :
Advanced Research in Asynchronous Circuits and Systems, 1997. Proceedings., Third International Symposium on
Conference_Location :
Eindhoven
Print_ISBN :
0-8186-7922-0
DOI :
10.1109/ASYNC.1997.587169
