Title :
Bundled data asynchronous multipliers with data dependent computation times
Author :
Kearney, David ; Bergmann, Neil W.
Author_Institution :
Sch. of Phys. & Electron. Syst. Eng., South Australia Univ., SA, Australia
Abstract :
A novel asynchronous design method is introduced which combines the area efficiency of bundled data with data dependent computation time. The design of a 16×16 bit multiplier using this technique is explained and evaluated. Simulation results show that area time savings of 20% compared to an equivalent synchronous design can be achieved
Keywords :
asynchronous circuits; computational complexity; logic design; multiplying circuits; 16×16 bit multiplier; area time savings; asynchronous design; data asynchronous multipliers; data dependent computation time; Adders; Australia; Circuits; Data mining; Delay effects; Digital signal processing; Logic design; Physics computing; Rails; Very large scale integration;
Conference_Titel :
Advanced Research in Asynchronous Circuits and Systems, 1997. Proceedings., Third International Symposium on
Conference_Location :
Eindhoven
Print_ISBN :
0-8186-7922-0
DOI :
10.1109/ASYNC.1997.587174
