A FPGA implementation of hardware based accelerator for a generic algorithm

Finding an optimum function is not only a theoretical mathematical problem but also a particular engineering problem. Many aspects in the electrical and electronics field (by example: image processing, filter matching, optimization of network parameters, resources allocation) can be solved by finding a target function and his minimum or maximum. For such problems, usually an analytical solution is not available and iterative algorithms are used. An Algorithm based of “Brute Force” require a very large number of iterations, such be a big disadvantage, especially when the algorithm is used for NP (Nondeterministic Polynomial time) problems where complexity and time to solve are incising exponentially with a number of an input parameters. More efficient algorithm is a Genetic Algorithm (GA), which imitates the biological evolution process, finding the solution by mechanism of “natural selection”, where the strong has higher chances to survive. Appling such algorithm in real time systems requires special approach due to variable number of iterations preformed until a solution is found. In this paper, we present the implementation for a hardware-based accelerator for a GA that solves a specific NP task. The accelerator implemented on a FPGA to provide a high-speed solution for this particular problem, for using in a real time system. An enhanced GA algorithm to solve the TSP problem presented and results obtained by writing a complete C simulation are analyzed. Algorithms and VHDL programs for PRNG and fixed point real numbers arithmetic´s, required for full FPGA implementation of a GA algorithm, and developed in accordance with our target Altera development board, are presented also. In addition, some possible solutions to improve our solution are analyzed.