Title :
Input Vector Control efficiency in sub-micron CMOS technologies
Author :
Shurin, Dmitry ; Kvaktun, Evgeniy ; Fish, Alexander
Author_Institution :
Dept. of Electr. & Comput. Eng., Ben-Gurion Univ., Beer-Sheva, Israel
Abstract :
The efficiency of the Input Vector Control (IVC) method in sub-micron technologies is examined. The IVC is a well known method for leakage current reduction during standby mode in digital circuits. Using the IVC method, a unique combination of input signal values, also referred to as a Minimum Leakage Vector (MLV), can be found for every circuit to minimize its standby leakage currents. While the IVC method was thoroughly examined for old process nodes, its efficiency in sub-micron technologies has not been investigated. Increases in gate and sub-threshold leakages, as well as the introduction of Deep Sub-Micron (DSM) effects that accompany technology scaling, significantly affect the MLV of a digital gate. In this paper, the efficiency of IVC for basic CMOS gates was examined in 90 nm, 65 nm and 40 nm standard CMOS technologies. The impact of gate sizing on the MLV was studied at different process corners. Simulation results show that while the IVC method is still efficient for advanced technologies, a gate´s MLV is less stable with respect to the gate size and process variations.
Keywords :
CMOS digital integrated circuits; leakage currents; nanoelectronics; basic CMOS gates; deep submicron effects; digital circuits; input signal values; input vector control efficiency; leakage current reduction; minimum leakage vector; size 40 nm to 90 nm; submicron CMOS technology; subthreshold leakages; CMOS integrated circuits; CMOS technology; Gate leakage; Logic gates; Transistors; Very large scale integration; IVC; Input Vector Control; Low power; leakage reduction;
Conference_Titel :
Electrical and Electronics Engineers in Israel (IEEEI), 2010 IEEE 26th Convention of
Conference_Location :
Eliat
Print_ISBN :
978-1-4244-8681-6
DOI :
10.1109/EEEI.2010.5662154
