Title :
Design and performance verification of ALUs for 64-bit 8-issue superscaler microprocessors using 0.25 um CMOS technology
Author :
Wang, Chua-Chin ; Chen, Sheng-Hua ; Hsiao, Shen-Fu ; Wu, Chuan-Lin
Author_Institution :
Dept. of Electr. Eng., Nat. Sun Yat-Sen Univ., Kaohsiung, Taiwan
Abstract :
In this paper, we present designs of a set of four non-homogeneous ALUs which can be employed in the next generation 64-bit ×86-compatible microprocessors. The entire design is realized by synthesizable Verilog RTL (register-transfer level) code. The gate level code is generated by Synopsys using COMPASS 0.6 um 1P3M cell library, and UMC 0.25 um 1P5M cell library. The correctness of the functionality of the individual ALU is verified in both RTL code and gate level code after the synthesization
Keywords :
CMOS digital integrated circuits; computer architecture; integrated circuit design; logic CAD; microprocessor chips; 0.25 mum; 0.6 mum; 1P3M cell library; 64 bit; 8-issue superscaler microprocessors; ALU; CMOS technology; COMPASS; RTL code; Synopsys; UMC 1P5M cell library; Verilog RTL code; design; functionality; gate level code; register-transfer level code; Assembly; CMOS technology; Computer science; Design engineering; Hardware design languages; Libraries; Logic; Microprocessors; Parallel processing; Pipeline processing;
Conference_Titel :
Electronics, Circuits and Systems, 1999. Proceedings of ICECS '99. The 6th IEEE International Conference on
Conference_Location :
Pafos
Print_ISBN :
0-7803-5682-9
DOI :
10.1109/ICECS.1999.814388
