Speed improvement of ΣΔ modulators simulation at the device level

In the design of sigma-delta modulator A/D converters, device-level simulation using SPICE is usually used to do the final verification while system tools are used to optimize the circuit parameters. This is because of the intolerable time and memory requirement in the device-level simulation. This paper presents a method to reduce the simulation time so that modulator optimization can be carried out at the device-level. In the proposed method, the frequency of the test signal is much higher than that in the traditional way. A simple nonlinear model of the modulator is established to analyze the harmonic distortion in the simulation. An example of a second-order modulator shows that the simulation speed can be improved by about two orders of magnitude