Analytical modeling of short-circuit energy dissipation in submicron CMOS structures

In this paper, an accurate analytical model for the short-circuit energy dissipation of CMOS logic structures, on the basis of a CMOS inverter, is presented. The derived model is based on analytical expressions of the inverter output waveform which include the influences of both transistor currents and the gate-to-drain coupling capacitance. Also, the effect of the short-circuiting transistor´s gate-source capacitance on the short-circuit energy dissipation, is taken into account. The α-power law MOS model which considers the carriers´ velocity saturation effect of submicron devices, is used. The results produced by the suggested model for a commercial 0.8 μm process show very good agreement with SPICE simulations (error less than 15% in most cases). After the extension of the inverter model to CMOS gates, the accuracy is maintained at the same level