Abstract :
This article proposes a method which reduces delay and area in EDAC circuits. A SEC-DED Hsiao code (39,32) and a DEC systematic (1 6, 8) code used for the hardware implementation of EDAC, are discussed and compared. Two codes are all proposed by the authors in earlier paper. In terms of parity-check matrix of these codes, this article presents a low-cost generation method of check bits. Simulation results show the delay and area of check bits generator based on 2-input XOR gates structure in the smic 180 nm process case. EDAC for 32 bits data, SEC-DED Hsiao code(32,7) need less extra memory bits than DEC systematic (1 6, 8) code ,but SEC-DED Hsiao code(32,7) take more delay and area , Which show that different code and different implementation can affect the cost of EDAC circuitry and be used as a guide for selecting the proper Code for different application requirements.
Keywords :
error correction codes; error detection codes; logic circuits; parity check codes; radiation effects; 2-input XOR gates structure; EDAC circuitry; EDAC circuits; SEC-DED Hsiao code; check bits generator; hardware implementation; low-cost generation method; parity check matrix; Circuits; Costs; Delay; Electrical fault detection; Error correction; Error correction codes; Fault detection; Hardware; Parity check codes; Single event upset; Error detection and correction (EDAC); Single error correction and double error detection (SEC-DED) code; double error correction (DEC) code; hardware-implemention; memory fault tolerance; single error upset (SEU);
