Reduction in output DC offset voltage of integrator-based filters

Author

Wada, Kazuyoshi ; Takagi, Shinichi ; Fujii, Nobuo

Author_Institution

Dept. of Phys. Electron., Tokyo Inst. of Technol., Japan

Volume

2

fYear

1998

fDate

1998

Firstpage

17

Abstract

Integrator-based filter structures suitable for reduction in DC offset are proposed. First, the effect of DC offset is analyzed by the use of a state space equation. Offset of a filter is the sum of analysis results for all integrators. A simple expression of the filter offset is obtained. The proposed minimization technique of the filter offset derives a lot of filter structures. All the proposed structures for nth-order all-pole low-pass characteristics have the minimum worst-case offset and the minimum variance of offset. Two of the filter structures are chosen to demonstrate the effectiveness of the proposed method

Keywords

active filters; integrating circuits; linear network analysis; low-pass filters; minimisation; signal flow graphs; state-space methods; SFG; all-pole low-pass characteristics; filter offset; integrator-based filters; minimization technique; output DC offset voltage reduction; state space equation; Circuits; Electronic mail; Equations; Low pass filters; Minimization; Resistors; Signal generators; Space technology; State-space methods; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronics, Circuits and Systems, 1998 IEEE International Conference on

Conference_Location

Lisboa

Print_ISBN

0-7803-5008-1

Type

conf

DOI

10.1109/ICECS.1998.814812

Filename

814812