Title : 
An event-driven model for the SpiNNaker virtual synaptic channel
         
        
            Author : 
Rast, Alexander ; Galluppi, Francesco ; Davies, Sergio ; Plana, Luis A. ; Sharp, Thomas ; Furber, Steve
         
        
            Author_Institution : 
Sch. of Comput. Sci., Univ. of Manchester, Manchester, UK
         
        
        
            fDate : 
July 31 2011-Aug. 5 2011
         
        
        
        
            Abstract : 
Neural networks present a fundamentally different model of computation from conventional sequential hardware, making it inefficient for very-large-scale models. Current neuromorphic devices do not yet offer a fully satisfactory solution even though they have improved simulation performance, in part because of fixed hardware, in part because of poor software support. SpiNNaker introduces a different approach, the “neuromimetic” architecture, that maintains the neural optimisation of dedicated chips while offering FPGA-like universal configurability. Central to this parallel multiprocessor is an asynchronous event-driven model that uses interrupt-generating dedicated hardware on the chip to support real-time neural simulation. In turn this requires an event-driven software model: a rethink as fundamental as that of the hardware. We examine this event-driven software model for an important hardware subsystem, the previously-introduced virtual synaptic channel. Using a scheduler-based system service architecture, the software can “hide” low-level processes and events from models so that the only event the model sees is “spike received”. Results from simulation on-chip demonstrate the robustness of the system even in the presence of extremely bursty, unpredictable traffic, but also expose important model-evel tradeoffs that are a consequence of the physical nature of the SpiNNaker chip. This event-driven subsystem is the first component of a library-based development system that allows the user to describe a model in a high-level neural description environment and be able to rely on a lower layer of system services to execute the model efficiently on SpiNNaker. Such a system realises a general-purpose platform that can generate an arbitrary neural network and run it with hardware speed and scale.
         
        
            Keywords : 
field programmable gate arrays; microprocessor chips; multiprocessing systems; neural nets; parallel architectures; virtual reality; FPGA-like universal configurability; SpiNNaker chip; SpiNNaker virtual synaptic channel; dedicated chip neural optimisation; event-driven model; event-driven software model; interrupt-generating dedicated hardware; library-based development system; neural networks; neuromimetic architecture; parallel multiprocessor; real-time neural simulation; scheduler-based system service architecture; simulation on-chip; Algorithms; Computational modeling; Computer aided manufacturing; Computer architecture; Routing; SDRAM; Switches;
         
        
        
        
            Conference_Titel : 
Neural Networks (IJCNN), The 2011 International Joint Conference on
         
        
            Conference_Location : 
San Jose, CA
         
        
        
            Print_ISBN : 
978-1-4244-9635-8
         
        
        
            DOI : 
10.1109/IJCNN.2011.6033466