A configurable zero stall pipelined image processor architecture for FPGAs

Today´s FPGAs are capable of performing complex Image Processing schemes. In this paper we introduce a Configurable Zero Stall Image-Processing Pipelined Architecture. We define the handshake and discuss limitation resulting from configurability and complexity. We then present our solution for these issues allowing a simple yet effective circuit where no delay is introduced even though the output and the input of each Processing Element are isolated through a Moore state machine.