DocumentCode
349751
Title
Design of low-power libraries
Author
Piguet, C.
Author_Institution
Centre Suisse d´´Electron. et de Microtechn. SA, Neuchatel, Switzerland
Volume
2
fYear
1998
fDate
1998
Firstpage
175
Abstract
The design of a low-power standard cell library has to satisfy several requirements, such as low activity of the internal nodes, reduced parasitic capacitances and the ability to work at very low Vdd. This paper presents some of these aspects with design examples of basic cells of a low-power library. This paper also presents a new method to design speed-independent cells starting from STG (Signal Transition Graphs)
Keywords
capacitance; cellular arrays; circuit CAD; graph theory; integrated circuit design; logic CAD; low-power electronics; STG; cell library design; low-power libraries; parasitic capacitances; signal transition graphs; speed-independent cells; standard cell library; Circuits; Delay; Design methodology; Energy consumption; Inverters; Libraries; Logic design; Logic gates; Parasitic capacitance; Signal design;
fLanguage
English
Publisher
ieee
Conference_Titel
Electronics, Circuits and Systems, 1998 IEEE International Conference on
Conference_Location
Lisboa
Print_ISBN
0-7803-5008-1
Type
conf
DOI
10.1109/ICECS.1998.814857
Filename
814857
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