Title :
HTDD based parallel fault simulator
Author :
Sapiecha, Joanna ; Sapiecha, Krzysztof ; Deniziak, Stanislaw
Author_Institution :
Dept. of Comput. Eng., Cracoe Univ. of Technol., Poland
Abstract :
In this paper a new efficient approach to bit-parallel fault simulation for sequential circuits is introduced and evaluated with the help of ISCAS89 benchmarks. Digital systems are modelled using Hierarchical Ternary Decision Diagrams (HTDDs). It leads to substantial reduction of both the number of simulated faults and calculations needed for simulation. Moreover, an approach presented in this paper is able to handle High-Level Primitives (HLPs) in addition to simple gates (GLPs), so it can be applied for hierarchical and multi-level simulation
Keywords :
automatic testing; binary decision diagrams; fault simulation; logic testing; sequential circuits; HTDD; Hierarchical Ternary Decision Diagrams; ISCAS89 benchmarks; bit-parallel fault simulation; hierarchical simulation; high-level primitives; multilevel simulation; parallel fault simulator; sequential circuits; simulated faults; Binary decision diagrams; Boolean functions; Circuit faults; Circuit simulation; Circuit testing; Computational modeling; Data structures; Digital systems; Sequential circuits; System testing;
Conference_Titel :
Electronics, Circuits and Systems, 1998 IEEE International Conference on
Conference_Location :
Lisboa
Print_ISBN :
0-7803-5008-1
DOI :
10.1109/ICECS.1998.814866
