Author_Institution :
Microprocessor R&D Center, Peking Univ., Beijing, China
Abstract :
Accurate branch prediction can improve processor performance, while reducing energy waste. Though some existing branch predictors have been proved effective, they usually require large amount of storage or complicate the processor front-end. This paper proposes a novel branch prediction technique called History Artificially Selected (HAS) prediction. It is a hardware technique that bases on the existing branch predictors to detect history noises and avoid noise interferences when predicting branches. It separates the original branch predictor into sub-predictors, each of which performs differently in branch history updating. With the help of some history stacks, one sub-predictor saves and restores the branch history at the entrance and the exit of loops and program subroutines where history noise usually exists. Through using a tournament mechanism, HAS prediction selectively uses the modified branch history to eliminate the history noise interferences and retain those useful history correlations at the same time. Our experimental results show that for three representative branch predictors, gshare, perceptron, and TAGE, it reduces the MPKI by 1.49, 2.85, and 1.10 respectively, resulting in 4.55%, 10.16%, and 4.45% performance improvement. It also reduces energy consumption by 4.02%, 7.78%, and 3.91%, respectively.
Keywords :
computer architecture; microprocessor chips; HAS prediction; TAGE; branch history; energy efficient branch prediction; global history noise reduction; gshare predictor; history artificially selected prediction; history noise interferences; perceptron; processor front-end; processor performance; Algorithms; Benchmark testing; Correlation; Hardware; History; Noise; Timing; Branch Prediction; Energy Efficient; History Noise;