A structure for extending the linear input voltage range of a differential input stage

This paper presents a method for extending the linear input voltage range of a differential input stage in weak inversion. This is accomplished using multiple differential pairs in parallel. To verify the function, a test circuit containing a four-quadrant multiplier was fabricated in a 1.2-μm n-well double-polysilicon, double metal CMOS process. This circuit operates with a ±1.5 V supply voltage, and I_dd=120 nA. A linear input voltage range of ±0.5 V with good linearity and less than 5% total harmonic distortion (THD) is achieved using 8 parallel-connected differential pairs. The design methodology as well as test results from the fabricated chip are discussed