DocumentCode
349791
Title
Using IEEE P1149.4
Author
Matos, José S. ; Da Silva, José Machado
Author_Institution
Fac. de Engenharia, Porto Univ., Portugal
Volume
2
fYear
1998
fDate
1998
Firstpage
441
Abstract
This paper reviews the special needs posed by today´s technological advances in boards and MCMs, and addresses the requirements they place on design for testability techniques for assemblies of complex chips, both digital and mixed-signal. The IEEE P1149.4 mixed-signal test infrastructure is briefly described and its use as a means to support and implement different DfT techniques is described. Actual results are shown of its use on the implementation of a mixed current/voltage testing technique
Keywords
IEEE standards; design for testability; integrated circuit testing; mixed analogue-digital integrated circuits; DfT techniques; IEEE P1149.4; design for testability techniques; mixed current/voltage testing technique; mixed-signal test infrastructure; Assembly; Automatic testing; Circuit testing; Costs; Design for testability; Fixtures; Integrated circuit modeling; Integrated circuit testing; System testing; Test equipment;
fLanguage
English
Publisher
ieee
Conference_Titel
Electronics, Circuits and Systems, 1998 IEEE International Conference on
Conference_Location
Lisboa
Print_ISBN
0-7803-5008-1
Type
conf
DOI
10.1109/ICECS.1998.814917
Filename
814917
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