• DocumentCode
    3497986
  • Title

    A review of large parallel counter designs

  • Author

    Swartzlander, Earl E., Jr.

  • Author_Institution
    Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA
  • fYear
    2004
  • fDate
    19-20 Feb. 2004
  • Firstpage
    89
  • Lastpage
    98
  • Abstract
    Parallel counters are key elements of many arithmetic elements, especially fast multipliers. This paper reviews a number of counter designs that have been presented over the last four decades. In this paper, the emphasis is on (7,3) counters.
  • Keywords
    arithmetic; counting circuits; multiplying circuits; parallel architectures; (7,3) counters; arithmetic elements; fast multipliers; parallel counter designs; Adders; CMOS logic circuits; Convolvers; Counting circuits; Delay; Digital arithmetic; Logic circuits; Relays; Signal processing; Very large scale integration;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI, 2004. Proceedings. IEEE Computer society Annual Symposium on
  • Print_ISBN
    0-7695-2097-9
  • Type

    conf

  • DOI
    10.1109/ISVLSI.2004.1339513
  • Filename
    1339513
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3497986