Title :
A trench isolation study for deep submicron CMOS technology
Author :
Chen, I.C. ; Rodder, M. ; Chatterjee, Avhishek ; Teng, C.W.
Author_Institution :
Texas Instruments, Dallas, TX, USA
Abstract :
The simple approach of thermal oxide capped poly refill trench isolation (Rung et al., 1982) is studied with regard to the impact of cap oxide thickness, trench wall thermal oxide thickness, and trench depth on MOSFET and isolation characteristics. It is shown that an increase of cap oxide thickness (tox) from 600 to 2000 AA eliminates subthreshold double-hump phenomena, improves isolation VT, improves inverse narrow-width effect, and still maintains reasonably low diode leakage current. An improvement of isolation VT is observed with thinner thermal oxide ( approximately 50 AA) on trench wall due to the less dopant segregation, while diode leakage is found to be insensitive to the trench wall thermal oxide thickness. The trade-off between latch-up holding and MOSFET snapback voltages leads to an optimal trench depth.
Keywords :
CMOS integrated circuits; insulated gate field effect transistors; integrated circuit technology; oxidation; 600 to 2000 angstroms; MOSFET snapback voltages; deep submicron CMOS technology; diode leakage current; dopant segregation; latch-up holding; optimal trench depth; thermal oxide capped poly refill trench isolation; trench wall thermal oxide thickness; CMOS process; CMOS technology; Doping; Etching; Implants; Isolation technology; MOSFET circuits; Plugs; Process design; Semiconductor diodes;
Conference_Titel :
VLSI Technology, Systems, and Applications, 1993. Proceedings of Technical Papers. 1993 International Symposium on
Conference_Location :
Taipei, Taiwan
Print_ISBN :
0-7803-0978-2
DOI :
10.1109/VTSA.1993.263595