A high performant 0.5 μm CMOS single chip ISDN network termination based on an embedded core and co-processor architecture

Narrowband ISDN (Integrated Services Digital Network) has been known for some years to be the next step in expanding the digital transmission capacity of the public telephone switching network. Currently there is a huge drive for highly integrated ISDN products, in particular for NT and LT applications. This paper describes a high performance single chip integration for NT applications, containing both the UkO- and SO-line interface circuits (UIC-SIC) on a single die. The key features of the chip architecture are: high performance analog front ends, the integration of an embedded ARM core, a dedicated digital signal processing co-processor. Specifically, the use of hardware-software co-design techniques is discussed in more detail. The chip is realized in an advanced 0.5 μm mixed analog-digital CMOS technology, and operates from a 3.3 V supply