DocumentCode
349806
Title
Efficient clock recovery architecture
Author
Mendez-Rivera, M. ; Valero-Lopez, A. ; Silva-Martinez, J. ; Sanchez-Sinencio, E.
Author_Institution
Integrated Circuit Design Group, Nat. Inst. of Astrophys., Opt. & Electron., Puebla, Mexico
Volume
2
fYear
1998
fDate
1998
Firstpage
537
Abstract
In this paper, a clock recovery architecture is proposed. Although it employs a single high frequency loop, the structure behaves as the typical double loop clock recovery system. The proposed topology uses a high frequency phase detector, a low frequency loop and avoids the use of quadrature VCOs
Keywords
data communication equipment; phase detectors; phase locked loops; synchronisation; HF data communication; clock recovery architecture; high frequency phase detector; low frequency loop; single high frequency loop; Astrophysics; Circuits; Clocks; Computational modeling; Equations; Filters; Frequency locked loops; Phase locked loops; Signal generators; Voltage-controlled oscillators;
fLanguage
English
Publisher
ieee
Conference_Titel
Electronics, Circuits and Systems, 1998 IEEE International Conference on
Conference_Location
Lisboa
Print_ISBN
0-7803-5008-1
Type
conf
DOI
10.1109/ICECS.1998.814939
Filename
814939
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