Sub-100 nm CMOS/SIMOX delay modeling by time-dependent gate capacitance model

Author

Lee, M. ; Asada, K.

Author_Institution

Dept. of Electron. Eng., Tokyo, Japan

fYear

1993

fDate

1993

Firstpage

242

Lastpage

246

Abstract

Contribution of the time-dependent gate capacitance (TDGC) model to CMOS/SIMOX inverter propagation delay time (TPD) in the deep sub-micrometer gate is studied. Results of theoretical prediction are compared with measurements of fifty-one stage ring oscillator TPDs. The TDGC model extends over conventional models in terms of worst- and best-case TPDs. It is predicted that the TDGC effect in the deep submicrometer regime will dominate when parasitic capacitances become relatively small as in future SOI technology.

Keywords

CMOS integrated circuits; SIMOX; delays; insulated gate field effect transistors; logic gates; semiconductor device models; CMOS/SIMOX delay modeling; CMOS/SIMOX inverter propagation delay time; SOI MOSFET; SOI technology; TDGC model; deep sub-micrometer gate; parasitic capacitances; ring oscillator; time-dependent gate capacitance model; Delay effects; Inverters; MOS devices; MOSFET circuits; Parasitic capacitance; Propagation delay; Semiconductor device modeling; Semiconductor films; Time measurement; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, Systems, and Applications, 1993. Proceedings of Technical Papers. 1993 International Symposium on

Conference_Location

Taipei, Taiwan

ISSN

1524-766X

Print_ISBN

0-7803-0978-2

Type

conf

DOI

10.1109/VTSA.1993.263597

Filename

263597