Energy-efficient pass-transistor-logic using decision feedback equalization

Decision feedback equalization (DFE) has been used to improve energy efficiency and/or reduce error rate in communication links. We propose a novel circuit technique which applies DFE techniques to pass transistor logic (PTL)-based computational circuits to mitigate errors, and reduce energy per computation or improve performance. We also present an optimization framework for designing low energy equalized PTL circuits that meet target performance and error rate specifications. On average, for the same operating frequency and error rate, the equalized PTL design consumes between 15% and 30% lower energy per operation than PTL and static complementary logic, respectively.