Title :
Multi-parameter power minimization of synthesized datapaths
Author :
Davis, W. Rhett ; Sule, Ambarish M. ; Hua, Hao
Author_Institution :
Dept. of Electr. & Comput. Eng., North Carolina State Univ., Raleigh, NC, USA
Abstract :
As processing technology continues to evolve, power minimization becomes more complex and crucial. Emerging technologies offer an array of different threshold voltages and gate oxide thicknesses. Along with choices of supply-voltage, parallelism, and pipelining, these options complicate the search for energy-optimal architectures. This paper explores the possibility of using convex optimization to solve the multi-parameter optimization problem and presents a case-study of an 8-bit multiply-accumulate block, which is optimized in 250nm and 70nm technologies.
Keywords :
accumulation layers; application specific integrated circuits; minimisation; multiplying circuits; power consumption; 250 nm; 70 nm; 8 bit; convex optimization; energy-optimal architectures; gate oxide thicknesses; multiparameter optimization problem; multiparameter power minimization; multiply-accumulate block; processing technology; synthesized datapaths; threshold voltages; Application specific integrated circuits; Design optimization; Energy efficiency; Libraries; Minimization; Parallel processing; Pipeline processing; System-on-a-chip; Threshold voltage; Very large scale integration;
Conference_Titel :
VLSI, 2004. Proceedings. IEEE Computer society Annual Symposium on
Print_ISBN :
0-7695-2097-9
DOI :
10.1109/ISVLSI.2004.1339523
