Multiplier design utilizing improved column compression tree and optimized final adder in CMOS technology

The authors discuss improvements in bit reduction techniques and a final adder which is optimized for the uneven signal arrival profile in a CMOS multiplier. Different architectures of the column compression counters and carry propagate adders which take advantage of the speed of the carry signal are considered. The configuration of column compression counters is optimized in order to reduce the longest signal path. The final adder is designed for the uneven input arrival time of the signals originating from the multiplier tree. This results in more compact wiring and balanced delays yielding a faster multiplier.