A fault-tolerant permutation network modulo arithmetic processor

Conventional fault-tolerant or fault detection of the modulo arithmetic processor are based on the properties of redundant residue number system which requires L redundant moduli to detect up to L errors and to correct up to L/2 errors. In this paper, the authors propose a new approach which can concurrently detect the errors of modulo processor based on the separate modulus by mixing the use of r-out-of-s residue codes and Berger codes. The result has a simpler architecture and can detect any number of module errors without any redundant moduli. In addition, it can tolerate L faults if L redundant moduli are used. Furthermore, the system also has the property of graceful degradation when the number of faulty modules exceeds L. Finally, the introduced cost for fault-tolerance is much less than those of previous published works.