A novel systolic architecture for the 2-D discrete Fourier transform

The two-dimensional discrete Fourier transform, (2-D DFT) is commonly employed in image processing systems. In this paper, a new systolic architecture is proposed for fast computation of the 2-D DFT. The system is constructed by using a recursive algorithm to compute the separable 2-D discrete Hartley transform (DHT) and then converting the result into the 2-D DFT. It possesses the features of regularity and modularity, and is thus well suited to VLSI implementation. As compared to the systolic 2-D DFT design described by Chen and Wang (1992), which reaches the lower bound of area-time complexity, the proposed one achieves the same throughput performance but saves the hardware complexity by a factor of 8.