DocumentCode
3498285
Title
VLSI implementation of single chip JPEG codec
Author
Chen, Meng-Hui ; Chen, Tzong-Kwei ; Chen, Yueh-Chang ; Pan, Jyh-Shin ; Weng, Yih-Shin
Author_Institution
Comput & Commun. Res. Labs., Industrial Technol. Res. Inst., Hsinchu, Taiwan
fYear
1993
fDate
1993
Firstpage
189
Lastpage
193
Abstract
This paper describes a single chip solution of the JPEG standard´s baseline system. A VLSI architecture is proposed to get better trade-off between chip size and performance. The IC is implemented in a 1.0 mu m CMOS process with a die size of 11.2*10.8 mm2.
Keywords
CMOS integrated circuits; VLSI; code standards; codecs; 1 micron; CMOS process; COMPASS design; JPEG standard baseline system; VLSI architecture; chip size; circuit layout; quantisation; single chip JPEG codec; Clocks; Codecs; Decoding; Discrete cosine transforms; Huffman coding; Image analysis; Image coding; Image quality; Pixel; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Technology, Systems, and Applications, 1993. Proceedings of Technical Papers. 1993 International Symposium on
Conference_Location
Taipei, Taiwan
ISSN
1524-766X
Print_ISBN
0-7803-0978-2
Type
conf
DOI
10.1109/VTSA.1993.263608
Filename
263608
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