Control and data flow graph extraction for high-level synthesis

The first step in high level synthesis consists of translating a behavioural specification into its corresponding register transfer language (RTL) description. Behavioural specifications are composed by writing code in a hardware description language such as VHDL. The process of translation starts by first deriving a control and data flow graph (CDFG) from the source code of the behavioural specification. The derivation of the CDFG has been mostly done manually, which makes this process time-consuming and error-prone at least in the earlier stage of synthesis. In this paper, we describe a tool that we have developed for automatic conversion of the given VHDL behavioural specification of a circuit into its corresponding CDFG. Since there is no widely accepted format for representing CDFGs, we opted to make the tool generate several representations of the derived CDFG in different formats to accommodate different implementation approaches. This design decision makes our tool quite flexible and highly useful. The proposed tool has been tested on operation and control-dominated behavioural specifications to ensure its accuracy. Experimental results on benchmark circuits show that the tool is highly accurate and can produce a CDFG in a few seconds using minimal computing resources.