Title :
I/O device drain engineering for a 5 V 0.6 mu m CMOS technology
Author :
Wei, Y. ; Loh, Y. ; Wang, C. ; Hu, C.
Author_Institution :
VLSI Technol. Inc., San Jose, CA, USA
Abstract :
The ESD robustness of LATID (Large Angle Tilted Implanted Drain) MOSFET for I/O drivers is evaluated and found inadequate for deep submicron 5 V CMOS technology. Alternative drain structures are examined and reported to meet the ESD and other criteria. An additional phosphorous implant that creates a LATID/DDD (Double Diffused Drain) structure meets all ESD and device criteria.
Keywords :
CMOS integrated circuits; VLSI; electrostatic discharge; integrated circuit technology; 0.6 micron; 5 V; CMOS technology; I/O device drain engineering; I/O drivers; LATID MOSFET; Si:P-SiO2; VLSI; double diffused drain; electrostatic discharge robustness; failure threshold; large angle tilted implanted drain; moderately doped drain; CMOS technology; Doping profiles; Drives; Electrostatic discharge; Implants; MOSFET circuits; Protection; Robustness; Variable structure systems; Very large scale integration;
Conference_Titel :
VLSI Technology, Systems, and Applications, 1993. Proceedings of Technical Papers. 1993 International Symposium on
Conference_Location :
Taipei, Taiwan
Print_ISBN :
0-7803-0978-2
DOI :
10.1109/VTSA.1993.263616
