Comparison of buried and surface channel PMOS devices for low voltage 0.5 mu m CMOS

A low voltage option in a 0.5 mu m CMOS process technology is described. The key technological issue is the threshold voltage and sub-threshold leakage characteristics of the PMOS devices. The device properties of the n⁺-gate buried channel devices are compared with the corresponding p⁺-gate surface channel devices. For power supply voltages down to 0.9 V the surface channel PMOS devices revealed superior transistor performance. Furthermore, the off-current characteristics are superior to the n⁺-gate buried channel devices. A minimum threshold voltage of -0.35 V of the 0.45 mu m physical gate length PMOS transistor with less then 0.1 nA/ mu m leakage current was realised in a 0.5 mu m CMOS process.