DocumentCode :
3498468
Title :
High performance 20-30 V LDMOS transistors in a 0.65 μm-based BiCMOS compatible process
Author :
Merchant, Steve ; Baird, Robert ; Hui, Paul ; Thoma, Rainer ; Victory, James
Author_Institution :
Motorola Inc., Mesa, AZ, USA
fYear :
1997
fDate :
28-30 Sep 1997
Firstpage :
202
Lastpage :
205
Abstract :
A 5th generation SMARTMOSTM 0.65 μm BiCMOS technology geared for advanced power applications yields the lowest specific on-resistance reported to date for the 20-30 V breakdown voltage range. A specific on-resistance of 0.34 mΩ-cm2 is achieved (VGS=10 V) for an avalanche breakdown voltage of 27 V. Experimental results are compared with numerical simulation and prior results in the literature. The effects of metal debiasing are also characterized
Keywords :
BiCMOS integrated circuits; avalanche breakdown; integrated circuit technology; power MOSFET; 0.65 micron; 20 to 30 V; BiCMOS technology; SMARTMOS 5AP; avalanche breakdown voltage; metal debiasing; power LDMOS transistor; specific on-resistance; Avalanche breakdown; BiCMOS integrated circuits; Breakdown voltage; Computational modeling; Doping profiles; Electrons; Ionization; Numerical simulation; Power generation; Transistors; Transportation;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Bipolar/BiCMOS Circuits and Technology Meeting, 1997. Proceedings of the
Conference_Location :
Minneapolis, MN
ISSN :
1088-9299
Print_ISBN :
0-7803-3916-9
Type :
conf
DOI :
10.1109/BIPOL.1997.647436
Filename :
647436
Link To Document :
https://search.ricest.ac.ir/dl/search/defaultta.aspx?DTC=49&DC=3498468
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