DocumentCode
3498538
Title
Buffer minimization in pipelined SDF scheduling on multi-core platforms
Author
Chen, Yuankai ; Zhou, Hai
Author_Institution
Electr. Eng. & Comput. Sci., Northwestern Univ., Evanston, IL, USA
fYear
2012
fDate
Jan. 30 2012-Feb. 2 2012
Firstpage
127
Lastpage
132
Abstract
With the increasing number of cores available on modern processors, it is imperative to solve the problem of mapping and scheduling a synchronous data flow graph onto a multi-core platform. Such a solution should not only meet the performance constraint, but also minimize resource usage. In this paper, we consider the pipeline scheduling problem for acyclic synchronous dataflow graph on a given number of cores to minimize the total buffer size while meeting the throughput constraint. We propose a two-level heuristic algorithm for this problem. The inner level finds the optimal buffer size for a given topological order of the input task graph; the outer level explores the space of topological order by applying perturbation to the topological order to improve buffer size. We compared our proposed algorithm to an enumeration algorithm which is able to generate optimal solution for small graphs, and a greedy algorithm which is able to run on large graphs. The experimental results show that our two-level heuristic algorithm achieves near-optimal solution compared to the enumeration algorithm, with only 0.8% increase in buffer size on average but with much shorter runtime, and achieves 38.8% less buffer usage on average, compared to the greedy algorithm.
Keywords
buffer storage; data flow computing; graph theory; greedy algorithms; multiprocessing systems; pipeline processing; processor scheduling; acyclic synchronous dataflow graph; buffer minimization; greedy algorithm; multicore platform; pipeline scheduling problem; pipelined synchronous dataflow scheduling; processor; synchronous data flow graph mapping; synchronous data flow graph scheduling; task graph; topological order; two-level heuristic algorithm; Dynamic programming; Heuristic algorithms; Partitioning algorithms; Processor scheduling; Program processors; Schedules; Throughput;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation Conference (ASP-DAC), 2012 17th Asia and South Pacific
Conference_Location
Sydney, NSW
ISSN
2153-6961
Print_ISBN
978-1-4673-0770-3
Type
conf
DOI
10.1109/ASPDAC.2012.6164932
Filename
6164932
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