DocumentCode
3498582
Title
Incorporating power reduction mechanism in arithmetic core design
Author
Hong, Sangjin ; Chin, Shu-Shin
Author_Institution
Dept. of Electr. & Comput. Eng., Stony Brook Univ., NY, USA
fYear
2004
fDate
19-20 Feb. 2004
Firstpage
249
Lastpage
250
Abstract
A novel supply voltage switching mechanism for reducing power dissipation of array structures is presented. The mechanism eliminates power dissipated by the glitching while it maintains the speed. The mechanism can be applied to either fully combinational or pipelined array structures such as parallel multipliers and/or CORDICs. The mechanism is easily incorporated such that no circuit change in the existing array structure is necessary.
Keywords
combinational switching; multiplying circuits; pipeline arithmetic; power supply circuits; CORDIC; arithmetic core design; combinational structures; glitching; parallel multipliers; pipelined array structures; power reduction mechanism; supply voltage switching mechanism; Adders; Arithmetic; Clocks; Delay; Logic arrays; Pipeline processing; Power dissipation; Registers; Switches; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI, 2004. Proceedings. IEEE Computer society Annual Symposium on
Print_ISBN
0-7695-2097-9
Type
conf
DOI
10.1109/ISVLSI.2004.1339544
Filename
1339544
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