COMET: a set of global transformation algorithms for high-level pipeline synthesis

The authors present a new systematic approach toward global hardware synthesis of DSP ASICs from behavioral specifications. A VHDL behavioral description is the input language of the COMET system. Given the stage time, data initialization interval (DII), and area-time tradeoff weight, a VHDL structural description is generated. A set of global data flow graph transformations is performed to minimize execution time of arithmetic expressions and to maximize conditonal resource sharing. Moreover, cluster structures derived from repeated pattern identification are used to guide global scheduling and allocation. The system provides the designer with a weight parameter to control the tradeoffs between area and time. With these transformations, major improvements are achieved with fewer registers and multiplexors; leading to a production quality design.