Title :
Test processor ASIC design
Author :
Ali, Md Liakot ; Darus, Zahari Mohamed ; Ali, Mohd Alauddin Mohd ; Ahmed, Iftekhar
Author_Institution :
Dept. of Electr. Electron. & Syst. Eng., Univ. Kebangsaan, Malaysia
Abstract :
In this paper, a design of a test processor ASIC employing a probabilistic approach is presented. The test processor chip is computer programmable. It consists of linear feedback shift register (LFSR) which can select one of 16 polynomials and set user programmable need for every test set, signature analyzer and 3 built-in RAMs and other control circuitry. It is capable of generating random numbers and applying them to the circuit under test (CUT) and then retrieve the responses from the CUT. It can generate a signature by compressing the response data and detect circuit faults by comparing this signature with that of a good CUT. This ASIC can be used to design a low cost IC tester of reliable performance
Keywords :
VLSI; application specific integrated circuits; automatic test equipment; automatic testing; built-in self test; digital signal processing chips; integrated circuit testing; logic testing; shift registers; LFSR; built-in RAMs; circuit fault detection; computer programmable tester; control circuitry; linear feedback shift register; low cost IC tester; polynomials selection; probabilistic approach; pseudorandom testing technique; random numbers generation; response data compression; signature analyzer; test processor ASIC design; test processor chip; test set; Application specific integrated circuits; Circuit testing; Electrical fault detection; Fault detection; Feedback circuits; Linear feedback control systems; Linear feedback shift registers; Polynomials; Process design; Random number generation;
Conference_Titel :
Semiconductor Electronics, 1996. ICSE '96. Proceedings., 1996 IEEE International Conference on
Conference_Location :
Penang
Print_ISBN :
0-7803-3388-8
DOI :
10.1109/SMELEC.1996.616494
